Memory devices are used in a wide range of fields. For example, solid-state memory can be used for long or short term storage of program instructions and data in connection with computing devices. Memory density, access speed, and reliability are all important considerations in designing solid-state memory. Recent solid-state memory designs have used three-dimensional architectures. Such designs can increase memory density. In addition, such designs are well suited for use in connection with resistive random access memory (ReRAM), and phase-change random access memory (PCRAM or PRAM).
In a three-dimensional (3D) memory structure, signal lines, including bit lines (BL) and word lines (WL), extend between socket regions on a periphery of the memory structure, and the memory array itself. More particularly, a first socket region on a first side of the memory array can include electrodes or contacts associated with the bit lines, and a second socket region on a second side of the memory array can include electrodes or contacts associated with the word lines. In other configurations, socket regions on first and second opposing sides of the memory array can be associated with bit lines, and socket regions on third and fourth opposing sides of the memory array can be associated with word lines. As the number of memory cells included in the memory array is increased, there is a corresponding increase in the number of signal lines (i.e. bit lines and/or word lines). In addition, due to physical constraints in the size of the bit lines and word lines, the area of the memory structure occupied by the socket regions becomes increasingly large as compared to an area of the memory array. This problem is exacerbated by decreases in the size of memory cells and in the size of memory cell pitch, and increases in the density of the memory array.
The area of the memory structure occupied by socket regions also increases relative to the area of the memory structure occupied by the memory array as the number of decks or layers within the memory structure increases. More particularly, in a conventional socket arrangement, different decks or layers, corresponding to different horizontal electrodes, are disposed in a staircase type arrangement. These different layers are accessed by vertical conductors. As a result, the size of the socket area must be increased in order to accommodate an increased number of horizontal electrodes. That is, the number of “stairs” in the “staircase” must be increased, which for a given electrode contact size results in a proportional increase in the length of the socket region in a direction extending away from the memory array. In addition, the size of a contact established between a horizontal electrode and a vertical conductor is constrained by various factors. For example, a minimum contact area needs to be maintained in order to provide a suitable electrical contact and thus a suitably low electrical resistance. In addition, the ability to align a vertical conductor with a desired contact area can be limited by manufacturing tolerances, thus requiring some minimum contact area margin. Therefore, the proportion of the total area occupied by connection or socket regions tends to become increasingly large as memory cell area density increases.
Because of such problems, decreases in the overall size of memory structures have not kept pace with decreases in the size of memory arrays themselves, and costs associated with providing three-dimensional memory structures have remained relatively high.